1. Field of the Invention
The present invention relates to a power supply having a function capable of switching between a full-wave rectification method and a voltage doubler rectification method according to an input voltage input from a commercial power supply.
2. Description of the Related Art
Japanese Patent Application Laid-Open No. 2000-316280 discusses a method for monitoring a voltage between a positive pole of an upper stage capacitor and a negative pole of a lower stage capacitor among two serially connected capacitors, as a configuration for protecting a smoothing capacitor provided to a power supply having a function capable of switching between a full-wave rectification method and a voltage doubler rectification method and a load connected to the power supply from an overvoltage. Further, Japanese Patent Application Laid-Open No. 2004-187391 discusses a configuration for monitoring an interterminal voltage of the upper stage capacitor and an interterminal voltage of the lower stage capacitor among the serially connected two capacitors, as a protecting configuration for protecting the capacitors from an overvoltage.
An example as discussed in Japanese Patent Application Laid-Open No. 2004-187391 for monitoring the interterminal voltage of the upper stage capacitor and the interterminal voltage of the lower stage capacitor among the serially connected two capacitors is described below with reference to FIG. 7. In such a power supply device, the full-wave rectification method and the voltage doubler rectification method are switched by a switch 3, and an alternating voltage input from a commercial power supply 1 is rectified by a bridge rectification circuit 2 (also referred to as diode bridge circuit). A general commercial power supply has two types such as a power supply of a 100V system for supplying about 100V and a power supply of a 200V system for supplying about 200V. In the former case, the switch 3 is turned on for the voltage doubler rectification and, whereas, in the letter case, the switch 3 is turned off for the full-wave rectification. Accordingly, smoothing capacitors 11 and 12 can be controlled such that the overvoltage is not applied to the smoothing capacitors 11 and 12.
Japanese Patent Application Laid-Open No. 2004-187391 also discusses a countermeasure against a case where the power supply of the 200V system is subjected to the voltage doubler rectification method. The countermeasure thereof is described below. In a case where a voltage between a positive pole of the smoothing capacitor 11 and a source of a field-effect transistor (FET) 13 excesses a predetermined threshold voltage, an interterminal voltage of a resistor 5 causes a shunt regulator 6 to turn on. After the shunt regulator 6 is turned on, transistors 8 and 7 are also turned on in this order. As a result thereof, a collector-emitter voltage of the transistor 7 drops and a gate-source voltage of the FET 13 drops below a gate threshold voltage, resulting in turning off of the FET 13. Accordingly, a current loop to the smoothing capacitor 11 is interrupted. A smoothing capacitor 12 can also be protected since the same protection circuit is provided to the smoothing capacitor 12 in a similar manner. More specifically, it is configured such that a voltage higher than a predetermined threshold is not applied to the smoothing capacitors 11 and 12 and a load 14, so that the smoothing capacitors 11 and 12 and the load 14 can be protected from an overvoltage.
However, in the conventional method for monitoring a voltage between the positive pole of the upper side capacitor and the negative pole of the lower side capacitor among the two serially connected capacitors 11 and 12, a countermeasure is not taken against the overvoltage applied to either one of the upper side capacitor or the lower side capacitor among the serially connected capacitors 11 and 12. On the other hand, with the method for monitoring an interterminal voltage of the upper stage capacitor and an interterminal voltage of the lower stage capacitor among the serially connected two capacitors 11 and 12, the countermeasure can be taken against the overvoltage applied to either one of the upper side capacitor and the lower side capacitor among the serially connected capacitors 11 and 12. However, a configuration in which a voltage applied to each of the two capacitors 11 and 12 is detected and a current loop to each capacitor is interrupted, as described above, raises the following problems.
The method requires two high breakdown voltage FETs and two high breakdown voltage transistors, resulting in inviting a high price.
The method requires the same two circuits in order to protect two capacitors 11 and 12, so that the method becomes expensive and the circuit size becomes larger.